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UNIT 4 Analog Circuits 2011 ONE MARK MCQ 4.1 In the circuit shown below, capacitors C1 and C2 are very large and are shorts at the input frequency. vi is a small signal input. The gain magnitude vo at 10 M rad/s is vi (A) maximum (B) minimum (C) unity (D) zero MCQ 4.2 The circuit below implements a filter between the input current ii and the output voltage vo . Assume that the op-amp is ideal. The filter implemented is a GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits (A) low pass filter (B) band pass filter (C) band stop filter (D) high pass filter 2011 TWO MARKS MCQ 4.3 In the circuit shown below, for the MOS transistors, n Cox = 100 A/V 2 and the threshold voltage VT = 1 V . The voltage Vx at the source of the upper transistor is (A) 1 V (B) 2 V (C) 3 V (D) 3.67 V MCQ 4.4 For a BJT, the common base current gain = 0.98 and the collector base junction reverse bias saturation current ICO = 0.6 A . This BJT is connected in the common emitter mode and operated in the active region with a base drive current IB = 20 A . The collector current IC for this mode of operation is (A) 0.98 mA (B) 0.99 mA (C) 1.0 mA (D) 1.01 mA Page 174 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.5 For the BJT, in the circuit shown below, Q1 = 3, VBEon = 0.7 V, VCEsat = 0.7 V . The switch is initially closed. At time t = 0 , the switch is opened. The time t at which Q1 leaves the active region is (A) 10 ms (B) 25 ms (C) 50 ms (D) 100 ms Statement for Linked Answer Questions: 4.6 & 4.7 In the circuit shown below, assume that the voltage drop across a forward biased diode is 0.7 V. The thermal voltage Vt = kT/q = 25 mV . The small signal input vi = Vp cos ^ t h where Vp = 100 mV. MCQ 4.6 The bias current IDC through the diodes is (A) 1 mA (B) 1.28 mA (C) 1.5 mA (D) 2 mA Page 175 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.7 The ac output voltage vac is (A) 0.25 cos ^ t h mV (B) 1 cos ( t) mV (C) 2 cos ( t) mV (D) 22 cos ( t) mV 2010 ONE MARK MCQ 4.8 The amplifier circuit shown below uses a silicon transistor. The capacitors CC and CE can be assumed to be short at signal frequency and effect of output resistance r0 can be ignored. If CE is disconnected from the circuit, which one of the following statements is true (A) The input resistance Ri increases and magnitude of voltage gain AV decreases (B) The input resistance Ri decreases and magnitude of voltage gain AV increases (C) Both input resistance Ri and magnitude of voltage gain AV decreases (D) Both input resistance Ri and the magnitude of voltage gain AV increases MCQ 4.9 In the silicon BJT circuit shown below, assume that the emitter area of transistor Q1 is half that of transistor Q2 Page 176 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits The value of current Io is approximately (A) 0.5 mA (B) 2 mA (C) 9.3 mA (D) 15 mA MCQ 4.10 Assuming the OP-AMP to be ideal, the voltage gain of the amplifier shown below is (A) R2 R1 (C) R2 | | R3 R1 (B) R 3 R1 (D) b R2 + R 3 l R1 2010 TWO MARKS Common Data Questions: 4.11 & 4.12 : Consider the common emitter amplifier shown below with the following circuit parameters: = 100, gm = 0.3861 A/V, r0 = 259 , RS = 1 k , RB = 93 k , RC = 250 k , RL = 1 k , C1 = 3 and C2 = 4.7 F Page 177 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.11 The resistance seen by the source vS is (A) 258 (B) 1258 (C) 93 k (D) 3 MCQ 4.12 The lower cut-off frequency due to C2 is (A) 33.9 Hz (B) 27.1 Hz (C) 13.6 Hz (D) 16.9 Hz MCQ 4.13 The transfer characteristic for the precision rectifier circuit shown below is (assume ideal OP-AMP and practical diodes) Page 178 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits 2009 TWO MARKS MCQ 4.14 In the circuit below, the diode is ideal. The voltage V is given by (A) min (Vi, 1) (B) max (Vi, 1) (C) min ( Vi, 1) (D) max ( Vi, 1) MCQ 4.15 In the following a stable multivibrator circuit, which properties of v0 (t) depend on R2 ? Page 179 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits (A) Only the frequency (B) Only the amplitude (C) Both the amplitude and the frequency (D) Neither the amplitude nor the frequency Statement for Linked Answer Question 4.16 and 4.17 Consider for CMOS circuit shown, where the gate voltage v0 of the n-MOSFET is increased from zero, while the gate voltage of the p MOSFET is kept constant at 3 V. Assume, that, for both transistors, the magnitude of the threshold voltage is 1 V and the product of the trans-conductance parameter is 1mA. V - 2 MCQ 4.16 For small increase in VG beyond 1V, which of the following gives the correct description of the region of operation of each MOSFET (A) Both the MOSFETs are in saturation region (B) Both the MOSFETs are in triode region (C) n-MOSFETs is in triode and p MOSFET is in saturation region (D) n- MOSFET is in saturation and p MOSFET is in triode region Page 180 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.17 Estimate the output voltage V0 for VG = 1.5 V. [Hints : Use the appropriate current-voltage equation for each MOSFET, based on the answer to Q.4.16] (A) 4 1 2 (C) 4 3 2 (B) 4 + 1 2 (D) 4 + 3 2 MCQ 4.18 In the circuit shown below, the op-amp is ideal, the transistor has VBE = 0.6 V and = 150 . Decide whether the feedback in the circuit is positive or negative and determine the voltage V at the output of the op-amp. (A) Positive feedback, V = 10 V. (B) Positive feedback, V = 0 V (C) Negative feedback, V = 5 V (D) Negative feedback, V = 2 V MCQ 4.19 A small signal source Vi (t) = A cos 20t + B sin 106 t is applied to a transistor amplifier as shown below. The transistor has = 150 and hie = 3 . Which expression best approximate V0 (t) Page 181 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits (A) V0 (t) = 1500 (A cos 20t + B sin 106 t) (B) V0 (t) = 1500( A cos 20t + B sin 106 t) (C) V0 (t) = 1500B sin 106 t (D) V0 (t) = 150B sin 106 t 2008 ONE MARK MCQ 4.20 In the following limiter circuit, an input voltage Vi = 10 sin 100 t is applied. Assume that the diode drop is 0.7 V when it is forward biased. When it is forward biased. The zener breakdown voltage is 6.8 V The maximum and minimum values of the output voltage respectively are (A) 6.1 V, 0.7 V (B) 0.7 V, 7.5 V (C) 7.5 V, 0.7 V (D) 7.5 V, 7.5 V Page 182 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits 2008 TWO MARSK MCQ 4.21 For the circuit shown in the following figure, transistor M1 and M2 are identical NMOS transistors. Assume the M2 is in saturation and the output is unloaded. The current Ix is related to Ibias as (A) Ix = Ibias + Is (B) Ix = Ibias (C) Ix = Ibias cVDD Vout m RE (D) Ix = Ibias Is MCQ 4.22 Consider the following circuit using an ideal OPAMP. The I-V characteristic of the diode is described by the relation I = I 0 _eV 1i where VT = 25 mV, I0 = 1 A and V is the voltage across the diode (taken as positive for forward bias). For an input voltage Vi = 1 V , the output voltage V0 is V t (A) 0 V (B) 0.1 V (C) 0.7 V (D) 1.1 V MCQ 4.23 The OPAMP circuit shown above represents a Page 183 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits (A) high pass filter (B) low pass filter (C) band pass filter (D) band reject filter MCQ 4.24 Two identical NMOS transistors M1 and M2 are connected as shown below. Vbias is chosen so that both transistors are in saturation. The equivalent gm of the pair is defied to be 2Iout at constant Vout 2Vi The equivalent gm of the pair is (A) the sum of individual gm ' s of the transistors (B) the product of individual gm s of the transistors (C) nearly equal to the gm of M1 (D) nearly equal to gm of M2 g0 MCQ 4.25 Consider the Schmidt trigger circuit shown below A triangular wave which goes from -12 to 12 V is applied to the inverting input of OPMAP. Assume that the output of the OPAMP swings from +15 V to -15 V. The voltage at the non-inverting input switches between Page 184 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits (A) 12V to +12 V (B) -7.5 V to 7.5 V (C) -5 V to +5 V (D) 0 V and 5 V Statement for Linked Answer Question 3.26 and 3.27: In the following transistor circuit, VBE = 0.7 V, r3 = 25 mV/IE , and and all the capacitances are very large MCQ 4.26 The value of DC current IE is (A) 1 mA (B) 2 mA (C) 5 mA (D) 10 mA MCQ 4.27 The mid-band voltage gain of the amplifier is approximately (A) -180 (B) -120 (C) -90 (D) -60 Page 185 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits 2007 ONE MARK MCQ 4.28 The correct full wave rectifier circuit is MCQ 4.29 In a transconductance amplifier, it is desirable to have (A) a large input resistance and a large output resistance (B) a large input resistance and a small output resistance (C) a small input resistance and a large output resistance (D) a small input resistance and a small output resistance 2007 TWO MARKS MCQ 4.30 For the Op-Amp circuit shown in the figure, V0 is (A) -2 V (B) -1 V (C) -0.5 V (D) 0.5 V Page 186 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.31 For the BJT circuit shown, assume that the of the transistor is very large and VBE = 0.7 V. The mode of operation of the BJT is (A) cut-off (B) saturation (C) normal active (D) reverse active MCQ 4.32 In the Op-Amp circuit shown, assume that the diode current follows the equation I = Is exp (V/VT ). For Vi = 2V, V0 = V01, and for Vi = 4V, V0 = V02 . The relationship between V01 and V02 is (A) V02 = 2 Vo1 (C) Vo2 = Vo1 1n2 (B) Vo2 = e2 Vo1 (D) Vo1 Vo2 = VT 1n2 MCQ 4.33 In the CMOS inverter circuit shown, if the trans conductance parameters of the NMOS and PMOS transistors are W kn = kp = n Cox Wn = Cox p = 40 A/V2 Ln Lp and their threshold voltages ae VTHn = VTHp = 1 V the current I is Page 187 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits (A) 0 A (B) 25 A (C) 45 A (D) 90 A MCQ 4.34 For the Zener diode shown in the figure, the Zener voltage at knee is 7 V, the knee current is negligible and the Zener dynamic resistance is 10 . If the input voltage (Vi) range is from 10 to 16 V, the output voltage (V0) ranges from (A) 7.00 to 7.29 V (B) 7.14 to 7.29 V (C) 7.14 to 7.43 V (D) 7.29 to 7.43 V Statement for Linked Answer Questions 4.35 & 4.36: Consider the Op-Amp circuit shown in the figure. MCQ 4.35 The transfer function V0 (s)/ Vi (s) is (A) 1 sRC (B) 1 + sRC 1 + sRC 1 sRC Page 188 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits (C) 1 1 sRC (D) 1 1 + sRC MCQ 4.36 If Vi = V1 sin ( t) and V0 = V2 sin ( t + ), then the minimum and maximum values of (in radians) are respectively (A) and (B) 0 and 2 2 2 (C) and 0 (D) and 0 2 2006 ONE MARK MCQ 4.37 The input impedance (Zi) and the output impedance (Z0) of an ideal trans-conductance (voltage controlled current source) amplifier are (A) Zi = 0, Z0 = 0 (B) Zi = 0, Z0 = 3 (C) Zi = 3, Z0 = 0 (D) Zi = 3, Z0 = 3 MCQ 4.38 An n-channel depletion MOSFET has following two points on its ID VGs curve: (i) VGS = 0 at ID = 12 mA and (ii) VGS = 6 Volts at ID = 0 mA Which of the following Q point will given the highest trans conductance gain for small signals? (A) VGS = 6 Volts (B) VGS = 3 Volts (C) VGS = 0 Volts (D) VGS = 3 Volts 2006 TWO MARKS MCQ 4.39 For the circuit shown in the following figure, the capacitor C is initially uncharged. At t = 0 the switch S is closed. The Vc across the capacitor at t = 1 millisecond is Page 189 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits In the figure shown above, the OP-AMP is supplied with ! 15V . (A) 0 Volt (B) 6.3 Volt (C) 9.45 Volts (D) 10 Volts MCQ 4.40 For the circuit shown below, assume that the zener diode is ideal with a breakdown voltage of 6 volts. The waveform observed across R is Common Data for Questions 4.41, 4.42 and 4.43 : In the transistor amplifier circuit shown in the figure below, the Page 190 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits transistor has the following parameters: DC = 60 , VBE = 0.7V, hie " 3 The capacitance CC can be assumed to be infinite. In the figure above, the ground has been shown by the symbol 4 MCQ 4.41 Under the DC conditions, the collector-or-emitter voltage drop is (A) 4.8 Volts (B) 5.3 Volts (C) 6.0 Volts (D) 6.6 Volts MCQ 4.42 If DC is increased by 10%, the collector-to-emitter voltage drop (A) increases by less than or equal to 10% (B) decreases by less than or equal to 10% (C) increase by more than 10% (D) decreases by more than 10% MCQ 4.43 The small-signal gain of the amplifier vc is vs (A) -10 (B) -5.3 (C) 5.3 (D) 10 Common Data for Questions 4.44 & 4.45: A regulated power supply, shown in figure below, has an unregulated input (UR) of 15 Volts and generates a regulated output Vout . Use the component values shown in the figure. Page 191 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.44 The power dissipation across the transistor Q1 shown in the figure is (A) 4.8 Watts (B) 5.0 Watts (C) 5.4 Watts (D) 6.0 Watts MCQ 4.45 If the unregulated voltage increases by 20%, the power dissipation across the transistor Q1 (A) increases by 20% (B) increases by 50% (C) remains unchanged (D) decreases by 20% 2005 ONE MARK MCQ 4.46 The input resistance Ri of the amplfier shown in the figure is (A) 30 k 4 (B) 10 k (C) 40 k (D) infinite Page 192 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.47 The effect of current shunt feedback in an amplifier is to (A) increase the input resistance and decrease the output resistance (B) increases both input and output resistance (C) decrease both input and output resistance (D) decrease the input resistance and increase the output resistance MCQ 4.48 The cascade amplifier is a multistage configuration of (A) CC CB (B) CE CB (C) CB CC (D) CE CC 2005 TWO MARKS MCQ 4.49 In an ideal differential amplifier shown in the figure, a large value of (RE ). (A) increase both the differential and common - mode gains. (B) increases the common mode gain only. (C) decreases the differential mode gain only. (D) decreases the common mode gain only. MCQ 4.50 For an npn transistor connected as shown in figure VBE = 0.7 volts. Given that reverse saturation current of the junction at room temperature 300 K is 10 - 13 A, the emitter current is (A) 30 mA (B) 39 mA (C) 49 mA (D) 20 mA Page 193 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.51 The voltage e0 is indicated in the figure has been measured by an ideal voltmeter. Which of the following can be calculated ? (A) Bias current of the inverting input only (B) Bias current of the inverting and non-inverting inputs only (C) Input offset current only (D) Both the bias currents and the input offset current MCQ 4.52 The Op-amp circuit shown in the figure is filter. The type of filter and its cut. Off frequency are respectively (A) high pass, 1000 rad/sec. (B) Low pass, 1000 rad/sec (C) high pass, 1000 rad/sec (D) low pass, 10000 rad/sec MCQ 4.53 The circuit using a BJT with = 50 and VBE = 0.7V is shown in the figure. The base current IB and collector voltage by VC and respectively Page 194 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits (A) 43 A and 11.4 Volts (B) 40 A and 16 Volts (C) 45 A and 11 Volts (D) 50 A and 10 Volts MCQ 4.54 The Zener diode in the regulator circuit shown in the figure has a Zener voltage of 5.8 volts and a zener knee current of 0.5 mA. The maximum load current drawn from this current ensuring proper functioning over the input voltage range between 20 and 30 volts, is (A) 23.7 mA (B) 14.2 mA (C) 13.7 mA (D) 24.2 mA MCQ 4.55 Both transistors T1 and T2 show in the figure, have a = 100 , threshold voltage of 1 Volts. The device parameters K1 and K2 of T1 and T2 are, respectively, 36 A/V2 and 9 A/V 2 . The output voltage Vo i s (A) 1 V (B) 2 V (C) 3 V (D) 4 V Page 195 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits Common Data Questions 4.58, 4.59 and 4.60 : Given, rd = 20k , IDSS = 10 mA, Vp = 8 V MCQ 4.56 Zi and Z0 of the circuit are respectively (A) 2 M and 2 k (B) 2 M and 20 k 11 (C) infinity and 2 M (D) infinity and 20 k 11 MCQ 4.57 ID and VDS under DC conditions are respectively (A) 5.625 mA and 8.75 V (B) 1.875 mA and 5.00 V (C) 4.500 mA and 11.00 V (D) 6.250 mA and 7.50 V MCQ 4.58 Transconductance in milli-Siemens (mS) and voltage gain of the amplifier are respectively (A) 1.875 mS and 3.41 (B) 1.875 ms and -3.41 (C) 3.3 mS and -6 (D) 3.3 mS and 6 MCQ 4.59 Given the ideal operational amplifier circuit shown in the figure indicate the correct transfer characteristics assuming ideal diodes with zero cut-in voltage. Page 196 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits 2004 ONE MARK MCQ 4.60 An ideal op-amp is an ideal (A) voltage controlled current source (B) voltage controlled voltage source (C) current controlled current source (D) current controlled voltage source MCQ 4.61 Voltage series feedback (also called series-shunt feedback) results in (A) increase in both input and output impedances Page 197 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits (B) decrease in both input and output impedances (C) increase in input impedance and decrease in output impedance (D) decrease in input impedance and increase in output impedance MCQ 4.62 The circuit in the figure is a (A) low-pass filter (B) high-pass filter (C) band-pass filter (D) band-reject filter 2004 TWO MARKS MCQ 4.63 A bipolar transistor is operating in the active region with a collector current of 1 mA. Assuming that the of the transistor is 100 and the thermal voltage (VT ) is 25 mV, the transconductance (gm) and the input resistance (r ) of the transistor in the common emitter configuration, are (A) gm = 25 mA/V and r = 15.625 k (B) gm = 40 mA/V and r = 4.0 k (C) gm = 25 mA/V and r = 2.5 k (D) gm = 40 mA/V and r = 2.5 k MCQ 4.64 The value of C required for sinusoidal oscillations of frequency 1 kHz in the circuit of the figure is Page 198 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits (A) 1 F 2 (C) 1 F 2 6 (B) 2 F (D) 2 6 F MCQ 4.65 In the op-amp circuit given in the figure, the load current iL is (A) Vs R2 (B) Vs R2 (C) Vs RL (D) Vs R1 MCQ 4.66 In the voltage regulator shown in the figure, the load current can vary from 100 mA to 500 mA. Assuming that the Zener diode is ideal (i.e., the Zener knee current is negligibly small and Zener resistance is zero in the breakdown region), the value of R is Page 199 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits (A) 7 (B) 70 (C) 70 3 (D) 14 MCQ 4.67 In a full-wave rectifier using two ideal diodes, Vdc and Vm are the dc and peak values of the voltage respectively across a resistive load. If PIV is the peak inverse voltage of the diode, then the appropriate relationships for this rectifier are (A) Vdc = Vm , PIV = 2Vm (B) Idc = 2 Vm , PIV = 2Vm (C) Vdc = 2 Vm , PIV = Vm (D) Vdc Vm , PIV = Vm MCQ 4.68 Assume that the of transistor is extremely large and VBE = 0.7V, IC and VCE in the circuit shown in the figure (A) IC = 1 mA, VCE = 4.7 V (B) IC = 0.5 mA, VCE = 3.75 V (C) IC = 1 mA, VCE = 2.5 V (D) IC = 0.5 mA, VCE = 3.9 V Page 200 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits 2003 ONE MARK MCQ 4.69 Choose the correct match for input resistance of various amplifier configurations shown below : Configuration Input resistance CB : Common Base LO : Low CC : Common Collector MO : Moderate CE : Common Emitter HI : High (A) CB LO, CC MO, CE HI (B) CB LO, CC HI, CE MO (C) CB MO, CC HI, CE LO (D) CB HI, CC LO, CE MO MCQ 4.70 The circuit shown in the figure is best described as a (A) bridge rectifier (B) ring modulator (C) frequency discriminator (D) voltage double MCQ 4.71 If the input to the ideal comparators shown in the figure is a sinusoidal signal of 8 V (peak to peak) without any DC component, then the output of the comparators has a duty cycle of (A) 1/2 (B) 1/3 (C) 1/6 (D) 1/2 Page 201 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.72 If the differential voltage gain and the common mode voltage gain of a differential amplifier are 48 dB and 2 dB respectively, then common mode rejection ratio is (A) 23 dB (B) 25 dB (C) 46 dB (D) 50 dB MCQ 4.73 Generally, the gain of a transistor amplifier falls at high frequencies due to the (A) internal capacitances of the device (B) coupling capacitor at the input (C) skin effect (D) coupling capacitor at the output 2003 TWO MARKS MCQ 4.74 An amplifier without feedback has a voltage gain of 50, input resistance of 1 k and output resistance of 2.5 k . The input resistance of the current-shunt negative feedback amplifier using the above amplifier with a feedback factor of 0.2, is (A) 1 k 11 (B) 1 k 5 (C) 5 k (D) 11 k MCQ 4.75 In the amplifier circuit shown in the figure, the values of R1 and R2 are such that the transistor is operating at VCE = 3 V and IC = 1.5 mA when its is 150. For a transistor with of 200, the operating point (VCE , IC ) is Page 202 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits (A) (2 V, 2 mA) (B) (3 V, 2 mA) (C) (4 V, 2 mA) (D) (4 V, 1 mA) MCQ 4.76 The oscillator circuit shown in the figure has an ideal inverting amplifier. Its frequency of oscillation (in Hz) is (A) 1 (2 6 RC) (B) 1 (2 RC) (C) 1 ( 6 RC) (D) 6 (2 RC) MCQ 4.77 The output voltage of the regulated power supply shown in the figure is Page 203 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits (A) 3 V (B) 6 V (C) 9 V (D) 12 V MCQ 4.78 If the op-amp in the figure is ideal, the output voltage Vout will be equal to (A) 1 V (B) 6 V (C) 14 V (D) 17 V MCQ 4.79 Three identical amplifiers with each one having a voltage gain of 50, input resistance of 1 k and output resistance of 250 are cascaded. The opened circuit voltages gain of the combined amplifier is (A) 49 dB (B) 51 dB (C) 98 dB (D) 102 dB MCQ 4.80 An ideal sawtooth voltages waveform of frequency of 500 Hz and amplitude 3 V is generated by charging a capacitor of 2 F in every cycle. The charging requires (A) Constant voltage source of 3 V for 1 ms (B) Constant voltage source of 3 V for 2 ms (C) Constant voltage source of 1 mA for 1 ms (D) Constant voltage source of 3 mA for 2 ms Page 204 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits 2002 ONE MARK MCQ 4.81 In a negative feedback amplifier using voltage-series (i.e. voltagesampling, series mixing) feedback. (A) Ri decreases and R0 decreases (B) Ri decreases and R0 increases (C) Ri increases and R0 decreases (D) Ri increases and R0 increases (Ri and R0 denote the input and output resistance respectively) MCQ 4.82 A 741-type opamp has a gain-bandwidth product of 1 MHz. A noninverting amplifier suing this opamp and having a voltage gain of 20 dB will exhibit a -3 dB bandwidth of (A) 50 kHz (B) 100 kHz (C) 1000 kHz 17 (D) 1000 kHz 7.07 MCQ 4.83 Three identical RC-coupled transistor amplifiers are cascaded. If each of the amplifiers has a frequency response as shown in the figure, the overall frequency response is as given in Page 205 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits 2002 TWO MARKS MCQ 4.84 The circuit in the figure employs positive feedback and is intended to generate sinusoidal oscillation. If at a frequency V (f) 1 f0, B (f) = 3 f = +0c, then to sustain oscillation at this frequency V0 (f) 6 (A) R2 = 5R1 (C) R2 = R1 6 (B) R2 = 6R1 (D) R2 = R1 5 MCQ 4.85 An amplifier using an opamp with a slew-rate SR = 1 V/ sec has Page 206 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits a gain of 40 dB. If this amplifier has to faithfully amplify sinusoidal signals from dc to 20 kHz without introducing any slew-rate induced distortion, then the input signal level must not exceed. (A) 795 mV (B) 395 mV (C) 79.5 mV (D) 39.5 mV MCQ 4.86 A zener diode regulator in the figure is to be designed to meet the specifications: IL = 10 mA V0 = 10 V and Vin varies from 30 V to 50 V. The zener diode has Vz = 10 V and Izk (knee current) =1 mA. For satisfactory operation (A) R # 1800 (B) 2000 # R # 2200 (C) 3700 # R # 4000 (D) R $ 4000 MCQ 4.87 The voltage gain Av = v0 of the JFET amplifier shown in the figure vt is IDSS = 10 mA Vp = 5 V(Assume C1, C2 and Cs to be very large (A) +16 (B) -16 (C) +8 (D) -6 Page 207 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits 2001 ONE MARK MCQ 4.88 The current gain of a BJT is (A) gm r0 (B) gm r (C) gm r (D) gm r MCQ 4.89 Thee ideal OP-AMP has the following characteristics. (A) Ri = 3, A = 3, R0 = 0 (B) Ri = 0, A = 3, R0 = 0 (C) Ri = 3, A = 3, R0 = 3 (D) Ri = 0, A = 3, R0 = 3 MCQ 4.90 Consider the following two statements : Statement 1 : A stable multi vibrator can be used for generating square wave. Statement 2: Bistable multi vibrator can be used for storing binary information. (A) Only statement 1 is correct (B) Only statement 2 is correct (C) Both the statements 1 and 2 are correct (D) Both the statements 1 and 2 are incorrect 2001 TWO MARKS MCQ 4.91 An npn BJT has gm = 38 mA/V, C = 10 14 F, C = 4 # 10 13 F, and DC current gain 0 = 90 . For this transistor fT and f are (A) fT = 1.64 # 108 Hz and f = 1.47 # 1010 Hz (B) fT = 1.47 # 1010 Hz and f = 1.64 # 108 Hz (C) fT = 1.33 # 1012 Hz and f = 1.47 # 1010 Hz (D) fT = 1.47 # 1010 Hz and f = 1.33 # 1012 Hz Page 208 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.92 The transistor shunt regulator shown in the figure has a regulated output voltage of 10 V, when the input varies from 20 V to 30 V. The relevant parameters for the zener diode and the transistor are : Vz = 9.5 , VBE = 0.3 V, = 99 , Neglect the current through RB . Then the maximum power dissipated in the zener diode (Pz ) and the transistor (PT ) are (A) Pz = 75 mW, PT = 7.9 W (B) Pz = 85 mW, PT = 8.9 W (C) Pz = 95 mW, PT = 9.9 W (D) Pz = 115 mW, PT = 11.9 W MCQ 4.93 The oscillator circuit shown in the figure is 4 (A) Hartely oscillator with foscillation = 79.6 MHz (B) Colpitts oscillator with foscillation = 50.3 MHz (C) Hartley oscillator with foscillation = 159.2 MHz (D) Colpitts oscillator with foscillation = 159.3 MHz Page 209 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.94 The inverting OP-AMP shown in the figure has an open-loop gain of 100. The closed-loop gain V0 is Vs (A) 8 (B) 9 (C) 10 (D) 11 MCQ 4.95 In the figure assume the OP-AMPs to be ideal. The output v0 of the circuit is (A) 10 cos (100t) (C) 10 - 4 # cos (100 ) d 0 t 2000 (B) 10 # cos (100 ) d 0 t (D) 10 - 4 d cos (100t) dt ONE MARK MCQ 4.96 In the differential amplifier of the figure, if the source resistance of the current source IEE is infinite, then the common-mode gain is Page 210 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits (A) zero (C) indeterminate (B) infinite (D) Vin1 + Vin2 2VT MCQ 4.97 In the circuit of the figure, V0 is (A) -1 V (B) 2 V (C) +1 V (D) +15 V MCQ 4.98 Introducing a resistor in the emitter of a common amplifier stabilizes the dc operating point against variations in (A) only the temperature (B) only the of the transistor (C) both temperature and (D) none of the above MCQ 4.99 The current gain of a bipolar transistor drops at high frequencies because of (A) transistor capacitances (B) high current effects in the base (C) parasitic inductive elements (D) the Early effect Page 211 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.100 If the op-anp in the figure, is ideal, then v0 is (A) zero (B) (V1 V2) sin t (C) (V1 + V2) sin t (D) (V1 + V2) sin t MCQ 4.101 The configuration of the figure is a (A) precision integrator (B) Hartely oscillator (C) Butterworth high pass filter (D) Wien-bridge oscillator MCQ 4.102 Assume that the op-amp of the figure is ideal. If vi is a triangular wave, then v0 will be (A) square wave (B) triangular wave (C) parabolic wave (D) sine wave Page 212 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.103 The most commonly used amplifier is sample and hold circuits is (A) a unity gain inverting amplifier (B) a unity gain non-inverting amplifier (C) an inverting amplifier with a gain of 10 (D) an inverting amplifier with a gain of 100 2000 TWO MARKS MCQ 4.104 In the circuit of figure, assume that the transistor is in the active region. It has a large and its base-emitter voltage is 0.7 V. The value of Ic is (A) Indeterminate since Rc is not given (B) 1 mA (C) 5 mA (D) 10 mA MCQ 4.105 If the op-amp in the figure has an input offset voltage of 5 mV and an open-loop voltage gain of 10000, then v0 will be (A) 0 V (B) 5 mV (C) + 15 V or -15 V (D) +50 V or -50 V Page 213 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits 1999 ONE MARK MCQ 4.106 The first dominant pole encountered in the frequency response of a compensated op-amp is approximately at (A) 5 Hz (B) 10 kHz (C) 1 MHz (D) 100 MHz MCQ 4.107 Negative feedback in an amplifier (A) reduces gain (B) increases frequency and phase distortions (C) reduces bandwidth (D) increases noise MCQ 4.108 In the cascade amplifier shown in the given figure, if the commonemitter stage (Q1) has a transconductance gm1 , and the common base stage (Q2) has a transconductance gm2 , then the overall transconductance g (= i 0 /vi) of the cascade amplifier is (A) gm1 (C) gm1 2 (B) gm2 (D) gm2 2 MCQ 4.109 Crossover distortion behavior is characteristic of (A) Class A output stage (B) Class B output stage (C) Class AB output stage (D) Common-base output stage Page 214 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits 1999 TWO MARK MCQ 4.110 An amplifier has an open-loop gain of 100, an input impedance of 1 k ,and an output impedance of 100 . A feedback network with a feedback factor of 0.99 is connected to the amplifier in a voltage series feedback mode. The new input and output impedances, respectively, are (B) 10 and 10 k (A) 10 and 1 (C) 100 k and 1 (D) 100 k and 1 k MCQ 4.111 A dc power supply has a no-load voltage of 30 V , and a full-load voltage of 25 V at a full-load current of 1 A . Its output resistance and load regulation, respectively, are (B) 25 and 20% (A) 5 and 20% (C) 5 and 16.7% (D) 25 and 16.7% 1998 ONE MARK MCQ 4.112 The circuit of the figure is an example of feedback of the following type (A) current series (B) current shunt (C) voltage series (D) voltage shunt MCQ 4.113 In a differential amplifier, CMRR can be improved by using an increased (A) emitter resistance (B) collector resistance (C) power supply voltages (D) source resistance Page 215 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.114 From a measurement of the rise time of the output pulse of an amplifier whose is a small amplitude square wave, one can estimate the following parameter of the amplifier (A) gain-bandwidth product (B) slow rate (C) upper 3 dB frequency (D) lower 3 dB frequency MCQ 4.115 The emitter coupled pair of BJT s given a linear transfer relation between the differential output voltage and the differential output voltage and the differential input voltage Vid is less times the thermal voltage, where is (A) 4 (B) 3 (C) 2 (D) 1 MCQ 4.116 In a shunt-shunt negative feedback amplifier, as compared to the basic amplifier (A) both, input and output impedances,decrease (B) input impedance decreases but output impedance increases (C) input impedance increase but output (D) both input and output impedances increases. 1998 TWO MARKS MCQ 4.117 A multistage amplifier has a low-pass response with three real poles at s = 1 2 and 3 . The approximate overall bandwidth B of the amplifier will be given by (A) B = 1 + 2 + 3 (B) 1 = 1 + 1 + 1 1 2 3 B (C) B = ( 1 + 2 + 3) 1/3 (D) B = 2 1 + 2 + 2 2 3 MCQ 4.118 One input terminal of high gain comparator circuit is connected to ground and a sinusoidal voltage is applied to the other input. The Page 216 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits output of comparator will be (A) a sinusoid (B) a full rectified sinusoid (C) a half rectified sinusoid (D) a square wave MCQ 4.119 In a series regulated power supply circuit, the voltage gain Av of the pass transistor satisfies the condition (A) Av " 3 (B) 1 << Av < 3 (C) Av . 1 (D) Av << 1 MCQ 4.120 For full wave rectification, a four diode bridge rectifier is claimed to have the following advantages over a two diode circuit : (A) less expensive transformer, (B) smaller size transformer, and (C) suitability for higher voltage application. Of these, (A) only (1) and (2) are true (B) only (1) and (3) are true (C) only (2) and (3) are true (D) (1), (2) as well as (3) are true MCQ 4.121 In the MOSFET amplifier of the figure is the signal output V1 and V2 obey the relationship (A) V1 = V2 2 (B) V1 = V2 2 (C) V1 = 2V2 (D) V1 = 2V2 Page 217 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.122 For small signal ac operation, a practical forward biased diode can be modelled as (A) a resistance and a capacitance in series (B) an ideal diode and resistance in parallel (C) a resistance and an ideal diode in series (D) a resistance 1997 ONE MARK MCQ 4.123 In the BJT amplifier shown in the figure is the transistor is based in the forward active region. Putting a capacitor across RE will (A) decrease the voltage gain and decrease the input impedance (B) increase the voltage gain and decrease the input impedance (C) decrease the voltage gain and increase the input impedance (D) increase the voltage gain and increase the input impedance MCQ 4.124 A cascade amplifier stags is equivalent to (A) a common emitter stage followed by a common base stage (B) a common base stage followed by an emitter follower (C) an emitter follower stage followed by a common base stage (D) a common base stage followed by a common emitter stage Page 218 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.125 In a common emitter BJT amplifier, the maximum usable supply voltage is limited by (A) Avalanche breakdown of Base-Emitter junction (B) Collector-Base breakdown voltage with emitter open (BVCBO) (C) Collector-Emitter breakdown voltage with base open (BVCBO) (D) Zener breakdown voltage of the Emitter-Base junction 1997 TWO MARKS MCQ 4.126 In the circuit of in the figure is the current iD through the ideal diode (zero cut in voltage and forward resistance) equals (A) 0 A (B) 4 A (C) 1 A (D) None of the above MCQ 4.127 The output voltage V0 of the circuit shown in the figure is (A) 4 V (B) 6 V (C) 5 V (D) 5.5 V Page 219 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits MCQ 4.128 A half wave rectifier uses a diode with a forward resistance Rf . The voltage is Vm sin t and the load resistance is RL . The DC current is given by Vm (A) Vm (B) (R f + RL) 2 RL (C) 2Vm (D) Vm RL 1996 ONE MARK MCQ 4.129 In the circuit of the given figure, assume that the diodes are ideal and the meter is an average indicating ammeter. The ammeter will read (A) 0.4 2 A (B) 0.4 A (C) 0.8 A (D) 0.4 mamp MCQ 4.130 The circuit shown in the figure is that of (A) a non-inverting amplifier (B) an inverting amplifier (C) an oscillator (D) a Schmitt trigger Page 220 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits 1996 TWO MARKS MCQ 4.131 In the circuit shown in the given figure N is a finite gain amplifier with a gain of k , a very large input impedance, and a very low output impedance. The input impedance of the feedback amplifier with the feedback impedance Z connected as shown will be (A) Z b1 1 l k Z (C) (k 1) (B) Z (1 k) (D) Z (1 k) MCQ 4.132 A Darlington stage is shown in the figure. If the transconductance of c Q1 is gm1 and Q2 is gm2 , then the overall transconductance gmc ; i c E Tc vbe is given by (A) gm1 (B) 0.5 gm1 (C) gm2 (D) 0.5 gm2 MCQ 4.133 Value of R in the oscillator circuit shown in the given figure, so chosen that it just oscillates at an angular frequency of . The value of and the required value of R will respectively be Page 221 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits (A) 105 rad/ sec, 2 # 10 4 (B) 2 # 10 4 rad/ sec, 2 # 10 4 (C) 2 # 10 4 rad/ sec, 105 (D) 105 rad/ sec, 105 MCQ 4.134 A zener diode in the circuit shown in the figure is has a knee current of 5 mA , and a maximum allowed power dissipation of 300 mW . What are the minimum and maximum load currents that can be drawn safely from the circuit, keeping the output voltage V0 constant at 6 V ? (A) 0 mA, 180 mA (B) 5 mA, 110 mA (C) 10 mA, 55 mA (D) 60 mA, 180 mA *********** Page 222 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOLUTIONS SOL 4.1 For the parallel RLC circuit resonance frequency is, 1 r = 1 = = 10 M rad/s 6 LC 10 # 10 # 1 # 10 9 Thus given frequency is resonance frequency and parallel RLC circuit has maximum impedance at resonance frequency Gain of the amplifier is gm # (ZC RL) where ZC is impedance of parallel RLC circuit. At = r , ZC = R = 2 k = ZC max . Hence at this frequency ( r ), gain is which is Gain = = gm (ZC RL) = gm (2k 2k) = gm # 103 maximum. Therefore gain is maximum at r = 10 M rad/ sec . Hence (A) is correct option. r SOL 4.2 The given circuit is shown below : From diagram we can write Ii = Vo + Vo R1 sL1 Transfer function H (s) = Vo = sR1 L1 I1 R1 + sL1 j R 1 L 1 or H (j ) = R 1 + j L 1 At = 0 H (j ) = 0 At = 3 H (j ) = R1 = constant . Hence (D) is correct option. Hence HPF. Page 223 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.3 Given circuit is shown below. For transistor M2 , VGS = VG VS = Vx 0 = Vx VDS = VD VS = Vx 0 = Vx Since VGS VT = Vx 1 < VDS , thus M2 is in saturation. By assuming M1 to be in saturation we have IDS (M ) = IDS (M ) n C 0x C (4) (5 Vx 1) 2 = n 0x 1 (Vx 1) 2 2 2 1 2 4 (4 Vx ) 2 = (Vx 1) 2 or 2 (4 Vx ) = ! (Vx 1) Taking positive root, 8 2Vx = Vx 1 Vx = 3 V At Vx = 3 V for M1,VGS = 5 3 = 2 V < VDS . Thus our assumption is true and Vx = 3 V . Hence (C) is correct option. SOL 4.4 We have Now = 0.98 = = 4.9 1 In active region, for common emitter amplifier, ...(1) IC = IB + (1 + ) ICO Substituting ICO = 0.6 A and IB = 20 A in above eq we have, IC = 1.01 mA Hence (D) is correct option. Page 224 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.5 In active region Emitter voltage Emitter Current VBEon = 0.7 V VE = VB VBEon = 5.7 V V ( 10) 5.7 ( 10) IE = E = = 1 mA 4.3k 4.3k Now IC . IE = 1 mA Applying KCL at collector i1 = 0.5 mA Since i1 = C dVC dt or VC = 1 C i # i1 dt = C1 t ...(1) with time, the capacitor charges and voltage across collector changes from 0 towards negative. When saturation starts,VCE = 0.7 & VC =+ 5 V (across capacitor) Thus from (1) we get, + 5 = 0.5 mA T 5 A 6 or T = 5 # 5 # 103 = 50 m sec 0.5 # 10 Hence (C) is correct option. SOL 4.6 The current flows in the circuit if all the diodes are forward biased. In forward biased there will be 0.7 V drop across each diode. 12.7 4 (0.7) Thus IDC = = 1 mA 9900 Hence (A) is correct option. Page 225 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.7 The forward resistance of each diode is r = VT = 25 mV = 25 IC 1 mA 4 (r) Thus Vac = Vi # e 4 (r) + 9900 o = 100 mV cos ( t) 0.01 = 1 cos ( t) mV Hence (B) is correct option. SOL 4.8 The equivalent circuit of given amplifier circuit (when CE is connected, RE is short-circuited) Input impedance Ri = R B | | r Voltage gain AV = gm RC Now, if CE is disconnected, resistance RE appears in the circuit Input impedance R in = RB | | [r + ( + 1)] RE Input impedance increases gm RC Voltage gain Voltage gain decreases. AV = 1 + gm R E Hence (A) is correct option. SOL 4.9 Since, emitter area of transistor Q1 is half of transistor Q2 , so current IE = 1 IE and IB = 1 IB 2 2 1 2 1 2 Page 226 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits The circuit is as shown below : VB = 10 ( 0.7) = 9.3 V Collector current I1 = 0 ( 9.3) = 1 mA (9.3 k ) 1 = 700 (high), So IC . IE Applying KCL at base we have 1 IE = IB + IB 1 ( 1 + 1) IB = IB + IB I 1 = (700 + 1 + 1) B + IB 2 1 1 2 1 1 2 2 2 IB . 2 702 2 I 0 = IC = 2 : IB = 715 # 2 . 2 mA 702 2 2 Hence (B) is correct option. SOL 4.10 The circuit is as shown below : So, 0 Vi + 0 Vo = 0 R1 R2 Page 227 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits or Vo = R2 Vi R1 Hence (A) is correct option. SOL 4.11 By small signal equivalent circuit analysis Input resistance seen by source vs R in = vs = Rs + Rs | | rs is = (1000 ) + (93 k || 259 ) = 1258 Hence (B) is correct option. SOL 4.12 Cut-off frequency due to C2 1 fo = 2 (RC + RL) C2 1 fo = = 271 Hz 2 # 3.14 # 1250 # 4.7 # 10 6 Lower cut-off frequency f fL . o = 271 = 27.1 Hz 10 10 Hence (B) is correct option. SOL 4.13 The circuit is as shown below Page 228 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits Current I = 20 0 + Vi 0 = 5 + Vi 4R R R If I > 0, diode D2 conducts So, for 5 + VI > 0 & VI > 5, D2 conducts 2 Equivalent circuit is shown below Output is Vo = 0 . If I < 0 , diode D2 will be off 5 + VI < 0 & V < 5, D is off I 2 R The circuit is shown below 0 Vi + 0 20 + 0 Vo = 0 R 4R R or Vo = Vi 5 At Vi = 5 V, Vo = 0 At Vi = 10 V, Vo = 5 V Hence (B) is correct option. SOL 4.14 Let diode be OFF. In this case 1 A current will flow in resistor and voltage across resistor will be V = 1.V Diode is off, it must be in reverse biased, therefore Vi 1 > 0 " Vi > 1 Thus for Vi > 1 diode is off and V = 1V Page 229 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits Option (B) and (C) doesn t satisfy this condition. Let Vi < 1. In this case diode will be on and voltage across diode will be zero and V = Vi Thus V = min (Vi, 1) Hence (A) is correct option. SOL 4.15 The R2 decide only the frequency. Hence (A) is correct option SOL 4.16 For small increase in VG beyond 1 V the n channel MOSFET goes into saturation as VGS " + ive and p MOSFET is always in active region or triode region. Hence (D) is correct option. SOL 4.17 Hence (C) is correct option. SOL 4.18 The circuit is shown in fig below The voltage at non inverting terminal is 5 V because OP AMP is ideal and inverting terminal is at 5 V. Thus IC = 10 5 = 1 mA 5k VE = IE RE = 1m # 1.4k = 1.4V = 0.6 + 1.4 = 2V IE = IC Page 230 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits Thus the feedback is negative and output voltage is V = 2V . Hence (D) is correct option. SOL 4.19 The output voltage is V0 = Ar Vi . hfe RC Vi hie Here RC = 3 and hie = 3 k Thus V0 . 150 # 3k Vi 3k . 150 (A cos 20t + B sin 106 t) Since coupling capacitor is large so low frequency signal will be filtered out, and best approximation is V0 . 150B sin 106 t Hence (D) is correct option. SOL 4.20 For the positive half of Vi , the diode D1 is forward bias, D2 is reverse bias and the zener diode is in breakdown state because Vi > 6.8 . Thus output voltage is V0 = 0.7 + 6.8 = 7.5 V For the negative half of Vi, D2 is forward bias thus Then V0 = 0.7 V Hence (C) is correct option. SOL 4.21 By Current mirror, ^ L h2 Ibias W ^ L h1 Since MOSFETs are identical, W W Thus b L l =b L l 2 2 W Ix = Hence Ix = Ibias Hence (B) is correct option. SOL 4.22 The circuit is using ideal OPAMP. The non inverting terminal of OPAMP is at ground, thus inverting terminal is also at virtual ground. Page 231 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits Thus current will flow from -ive terminal (0 Volt) to -1 Volt source. Thus the current I is 0 ( 1) I= =1 100k 100k The current through diode is I = I 0 _eV 1i Now VT = 25 mV and I0 = 1 A V t Thus V I = 10 6 8e 25 # 10 1B = 1 5 10 3 or V = 0.06 V Now V0 = I # 4k + V = 1 # 4k + 0.06 = 0.1 V 100k Hence (B) is correct option. SOL 4.23 The circuit is using ideal OPAMP. The non inverting terminal of OPAMP is at ground, thus inverting terminal is also at virtual ground. Thus we can write vi = v R R1 + sL sR C + 1 v0 = R2 or vi (R1 + sL)( sR2 C2 + 1) 2 2 2 and from this equation it may be easily seen that this is the standard form of T.F. of low pass filter Page 232 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits H (s) = K (R1 + sL)( sR2 C2 + 1) and form this equation it may be easily seen that this is the standard form of T.F. of low pass filter H (s) = 2 K as + bs + b Hence (B) is correct option. SOL 4.24 The current in both transistor are equal. Thus gm is decide by M1. Hence (C) is correct option. SOL 4.25 Let the voltage at non inverting terminal be V1, then after applying KCL at non inverting terminal side we have 15 V1 + V0 V1 = V1 ( 15) 10 10 10 or V1 = V0 3 If V0 swings from -15 to +15 V then V1 swings between -5 V to +5 V. Hence (C) is correct option. SOL 4.26 For the given DC values the Thevenin equivalent circuit is as follows The thevenin resistance and voltage are VTH = 10 # 9 = 3 V 10 + 20 and total RTH = 10k # 20k = 6.67 k 10k + 20k Page 233 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits Since is very large, therefore IB is small and can be ignored Thus IE = VTH VBE = 3 0.7 = 1 mA RE 2.3k Hence (A) is correct option. SOL 4.27 The small signal model is shown in fig below gm = IC = 1m = 1 A/V VT 25m 25 Vo = gm V # (3k 3k ) = 1 Vin (1.5k) 25 or IC . IE V = Vin = 60Vin Am = Vo = 60 Vin Hence (D) is correct option. SOL 4.28 The circuit shown in (C) is correct full wave rectifier circuit. Hence (C) is correct option. SOL 4.29 In the transconductance amplifier it is desirable to have large input resistance and large output resistance. Hence (A) is correct option. Page 234 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.30 We redraw the circuit as shown in fig. Applying voltage division rule v+ = 0.5 V We know that v+ = v- Thus v- = 0.5 V i = 1 0.5 = 0.5 mA 1k Now and or i = 0.5 v0 = 0.5 mA 2k v0 = 0.5 1 = 0.5 V Hence (C) is correct option. SOL 4.31 If we assume very large, then IB = 0 and IE = IC ; VBE = 0.7 V. We assume that BJT is in active, so applying KVL in Base-emitter loop IE = 2 VBE = 2 0.7 = 1.3 mA 1k RE Since is very large, we have IE = IC , thus IC = 1.3 mA Now applying KVL in collector-emitter loop 10 10IC VCE IC = 0 or VCE = 4.3 V Now VBC = VBE VCE = 0.7 ( 4.3) = 5 V Since VBC > 0.7 V, thus transistor in saturation. Hence (B) is correct option. Page 235 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.32 Here the inverting terminal is at virtual ground and the current in resistor and diode current is equal i.e. IR = ID Vi = I eV /V or s R or VD = VT 1n Vi Is R D T For the first condition VD = 0 Vo1 = VT 1n 2 Is R For the first condition VD = 0 Vo1 = VT 1n 4 Is R Subtracting above equation or Vo1 Vo2 = VT 1n 4 VT 1n 2 Is R Is R Vo1 Vo2 = VT 1n 4 = VT 1n2 2 Hence (D) is correct option. SOL 4.33 We have and Vthp = Vthp = 1 V WP W = N = 40 A/V2 LP LN From figure it may be easily seen that Vas for each NMOS and PMOS is 2.5 V A Thus ID = K (Vas VT ) 2 = 40 2 (2.5 1) 2 = 90 A V Hence (D) is correct option. SOL 4.34 We have VZ = 7 volt, VK = 0, RZ = 10 Circuit can be modeled as shown in fig below Page 236 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits Since Vi is lies between 10 to 16 V, the range of voltage across 200 k V200 = Vi VZ = 3 to 9 volt The range of current through 200 k is 3 = 15 mA to 9 = 45 mA 200k 200k The range of variation in output voltage 15m # RZ = 0.15 V to 45m # RZ = 0.45 Thus the range of output voltage is 7.15 Volt to 7.45 Volt Hence (C) is correct option. SOL 4.35 The voltage at non-inverting terminal is V+ = Now 1 sC R+ 1 sC V- = V+ = Vi = 1 V 1 + sCR i 1 V 1 + sCR i Applying voltage division rule (V + Vi) V+ = R1 (V0 + Vi) = o R1 + R1 2 or or (V + Vi) 1 Vi = o 1 + sCR 2 Vo = 1 + 2 Vi 1 + sRC V0 = 1 sRC Vi 1 + sRC Hence (A) is correct option. SOL 4.36 V0 = H (s) = 1 sRC Vi 1 + sRC H (j ) = 1 j RC 1 + j RC +H (j ) = = tan - 1 RC tan - 1 RC = 2 tan - 2 RC Minimum value, min = (at " 3) Maximum value, max = 0( at = 0) Hence (C) is correct option. Page 237 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.37 In the transconductance amplifier it is desirable to have large input impedance and large output impedance. Hence (D) is correct option. SOL 4.38 Hence (C) is correct option. SOL 4.39 The voltage at inverting terminal is V = V+ = 10 V Here note that current through the capacitor is constant and that is I = V = 10 = 10 mA 1k 1k Thus the voltage across capacitor at t = 1 msec is 1m 1m VC = 1 # Idt = 1 # 10mdt = 10 4 C0 1 0 # dt = 10 V 0 Im Hence (D) is correct option. SOL 4.40 In forward bias Zener diode works as normal diode. Thus for negative cycle of input Zener diode is forward biased and it conducts giving VR = Vin . For positive cycle of input Zener diode is reversed biased when 0 < Vin < 6 , Diode is OFF and VR = 0 when Vin > 6 Diode conducts and voltage across diode is 6 V. Thus voltage across is resistor is VR = Vin 6 Only option (B) satisfy this condition. Hence (A) is correct option. SOL 4.41 The circuit under DC condition is shown in fig below Page 238 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits Applying KVL we have VCC RC (IC + IB) VCE = 0 and VCC RB IB VBE = 0 Substituting IC = IB in (1) we have VCC RC ( IB + IB) VCE = 0 Solving (2) and (3) we get VCE = VCC VCC VBE RB 1+ RC (1 + ) Now substituting values we get 12 0.7 VCE = 12 = 5.95 V 53 1+ 1 + (1 + 60) Hence (C) is correct option. ...(1) ...(2) ...(3) ...(4) SOL 4.42 We have ' = 110 # 60 = 66 100 Substituting ' = 66 with other values in (iv) in previous solutions 12 0.7 VCE = 12 = 5.29 V 53 1+ 1 + (1 + 66) Thus change is = 5.29 59.5 # 100 = 4.3% 5.95 Hence (B) is correct option. SOL 4.43 Hence (A) is correct option. SOL 4.44 The Zener diode is in breakdown region, thus V+ = VZ = 6 V = Vin Page 239 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits We know that or Rf R1 m = Vo = 6`1 + 12k j = 9 V 24k Vo = Vin c1 + Vout The current in 12 k branch is negligible as comparison to 10 . Thus Current IC . IE . = Vout = 9 = 0.9 A RL 10 Now VCE = 15 9 = 6 V The power dissipated in transistor is P = VCE IC = 6 # 0.9 = 5.4 W Hence (C) is correct option. SOL 4.45 If the unregulated voltage increase by 20%, them the unregulated voltage is 18 V, but the VZ = Vin = 6 remain same and hence Vout and IC remain same. There will be change in VCE Thus, VCE 18 9 = 9 V IC = 0.9 A Power dissipation P = VCE IC = 9 # 0.9 = 8.1 W Thus % increase in power is 8.1 5.4 # 100 = 50% 5.4 Hence (B) is correct option. SOL 4.46 Since the inverting terminal is at virtual ground, the current flowing through the voltage source is Is = Vs 10k Vs = 10 k = R or in Is Hence (B) is correct option. SOL 4.47 The effect of current shunt feedback in an amplifier is to decrease the input resistance and increase the output resistance as : Rif = Ri 1 + A Page 240 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits Rof = R0 (1 + A ) where Ri " Input resistance without feedback Rif " Input resistance with feedback. Hence (D) is correct option. SOL 4.48 The CE configuration has high voltage gain as well as high current gain. It performs basic function of amplifications. The CB configuration has lowest Ri and highest Ro . It is used as last step to match a very low impedance source and to drain a high impedance load Thus cascade amplifier is a multistage configuration of CE-CB Hence (B) is correct option SOL 4.49 Common mode gain ACM = RC 2RE And differential mode gain ADM = gm RC Thus only common mode gain depends on RE and for large value of RE it decreases. Hence (D) is correct option. SOL 4.50 IE = Is `e nV 1j = 10 - 13 c VBE T 0.7 1m = 49 mA e1 # 26 # 10 -3 Hence (C) is correct option. SOL 4.51 The circuit is as shown below Page 241 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits Writing equation for I have e 0 V = I 1M or e0 = I (1M) + V Writing equation for I+ we have 0 V+ = I+ 1M ...(1) or ...(2) V+ = I+ (1M) Since for ideal OPAMP V+ = V- , from (1) and (2) we have e0 = I (1M) I + (1M) = (I I+) (1M) = IOS (1M) Thus if e0 has been measured, we can calculate input offset current IOS only. Hence (C) is correct option. SOL 4.52 At low frequency capacitor is open circuit and voltage acr s noninverting terminal is zero. At high frequency capacitor act as short circuit and all input voltage appear at non-inverting terminal. Thus, this is high pass circuit. The frequency is given by 1 = 1000 rad/sec = 1 = 3 RC 1 # 10 # 1 # 10 - 6 Hence (C) is correct option. SOL 4.53 The circuit under DC condition is shown in fig below Applying KVL we have VCC RB IB VBE RE IE = 0 or VCC RB IB VBE RE ( + 1) IB = 0 Since IE = IB + IB Page 242 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits or IB = = VCC VBE RB + ( + 1) RE 20 0.7 = 40 A 430k + (50 + 1)1 k IC = IB = 50 # 40 = 2 mA VC = VCC RC IC = 20 2m # 2k = 16 V Hence (B) is correct option. Now SOL 4.54 The maximum load current will be at maximum input voltage i.e. Vmax = 30 V i.e. Vmax VZ = I + I L Z 1k or 30 5.8 = I = 0.5 m L 1k or IL = 24.2 0.5 = 23.7 mA Hence (A) iscorrect option. SOL 4.55 Hence (D) is correct option. SOL 4.56 The small signal model is as shown below From the figure we have Zin = 2 M and Z0 = rd RD = 20k 2k = 20 k 11 Hence (B) is correct option. Page 243 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.57 The circuit in DC condition is shown below Since the FET has high input resistance, gate current can be neglect and we get VGS = 2 V Since VP < VGS < 0 , FET is operating in active region 2 ( 2) 2 Now ID = IDSS c1 VGS m = 10 c1 = 5.625 mA ( 8) m VP Now VDS = VDD ID RD = 20 5.625 m # 2 k = 8.75 V Hence (A) is correct option. SOL 4.58 The transconductance is gm = or, The gain is So, 2 ID IDSS VP = 2 5.625mA # 10mA = 1.875 mS 8 A = gm (rd RD) = 1.875ms # 20 K = 3.41 11 Hence (B) is correct option. SOL 4.59 Only one diode will be in ON conditions When lower diode is in ON condition, then Vu = 2k Vsat = 2 10 = 8 V 2.5k 2.5 when upper diode is in ON condition Vu = 2k Vsat = 2 ( 10) = 5 V 2.5k 4 Hence (B) is correct option. Page 244 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.60 An ideal OPAMP is an ideal voltage controlled voltage source. Hence (B) is correct option. SOL 4.61 In voltage series feed back amplifier, input impedance increases by factor (1 + A ) and output impedance decreases by the factor (1 + A ). Rif = Ri (1 + A ) Ro Rof = (1 + A ) Hence (C) is correct option. SOL 4.62 This is a Low pass filter, because V0 = 0 At = 3 Vin and at = 0 V0 = 1 Vin Hence (A) is correct option. SOL 4.63 When IC >> ICO gm = IC = 1mA = 0.04 = 40 mA/V VT 25mV = 100 - 3 = 2.5 k gm 40 # 10 Hence (D) is correct option. r = SOL 4.64 The given circuit is wein bridge oscillator. The frequency of oscillation is 2 f = 1 RC 1= 1 = 1 3 3 2 Rf 2 2 # 10 # 10 Hence (A) is correct option. or C= Page 245 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.65 The circuit is as shown below We know that for ideal OPAMP V- = V+ Applying KCL at inverting terminal V- Vs + V- V0 = 0 R1 R1 or 2V- Vo = Vs Applying KCL at non-inverting terminal V+ V Vo =0 + IL + + R2 R2 ...(1) or 2V+ Vo + IL R2 = 0 Since V- = V+ , from (1) and (2) we have Vs + IL R2 = 0 or IL = Vs R2 ...(2) Hence (A) is correct option. SOL 4.66 If IZ is negligible the load current is 12 Vz = I L R as per given condition 100 mA # 12 VZ # 500 mA R At IL = 100 mA 12 5 = 100 mA R VZ = 5 V R = 70 At IL = 500 mA 12 5 = 500 mA R VZ = 5 V or or R = 14 Page 246 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits Thus taking minimum we get R = 14 Hence (D) is correct option. SOL 4.67 Hence (B) is correct option. SOL 4.68 The thevenin equivalent is shown below VT = R1 V = 1 #5 = 1 R1 + R2 C 4+1 V Since is large is large, IC . IE , IB . 0 and IE = VT VBE = 1 0.7 = 3 mA RE 300 VCE = 5 2.2kIC 300IE = 5 2.2k # 1m 300 # 1m = 2.5 V Hence (C) is correct option Now SOL 4.69 For the different combinations the table is as follows CE CE CC CB Ai High High Unity Av High Unity High Ri Medium High Low Ro Medium Low High Hence (B) is correct option. Page 247 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.70 This circuit having two diode and capacitor pair in parallel, works as voltage doubler. Hence (D) is correct option. SOL 4.71 If the input is sinusoidal signal of 8 V (peak to peak) then Vi = 4 sin t The output of comparator will be high when input is higher than Vref = 2 V and will be low when input is lower than Vref = 2 V. Thus the waveform for input is shown below From fig, first crossover is at t1 and second crossover is at t2 where 4 sin t1 = 2V Thus t1 = sin - 1 1 = 2 6 t2 = = 5 6 6 Duty Cycle = 5 6 2 6 =1 3 Thus the output of comparators has a duty cycle of 1 . 3 Hence (B) is correct option. SOL 4.72 CMMR = Ad Ac or 20 log CMMR = 20 log Ad 20 log Ac = 48 2 = 46 dB Page 248 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits Where Ad " Differential Voltage Gain and AC " Common Mode Voltage Gain Hence (C) is correct option. SOL 4.73 The gain of amplifier is Ai = gm gb + j C Thus the gain of a transistor amplifier falls at high frequencies due to the internal capacitance that are diffusion capacitance and transition capacitance. Hence (B) is correct option. SOL 4.74 We have Ri = 1k , = 0.2, A = 50 Ri Thus, Rif = = 1 k (1 + A ) 11 Hence (A) is correct option. SOL 4.75 The DC equivalent circuit is shown as below. This is fixed bias circuit operating in active region. In first case VCC IC1 R2 VCE1 = 0 or 6 1.5mR2 3 = 0 or R2 = 2k IB1 = IC1 = 1.5m = 0.01 mA 1 150 In second case IB2 will we equal to IB1 as there is no in R1. Thus IC2 = 2 IB2 = 200 # 0.01 = 2 mA VCE2 = VCC IC2 R2 = 6 2m # 2 k = 2 V Hence (A) is correct option. Page 249 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.76 The given circuit is a R C phase shift oscillator and frequency of its oscillation is 1 f= 2 6 RC Hence (A) is correct option. SOL 4.77 If we see th figure we find that the voltage at non-inverting terminal is 3 V by the zener diode and voltage at inverting terminal will be 3 V. Thus Vo can be get by applying voltage division rule, i.e. 20 V = 3 20 + 40 o or V0 = 9 V Hence (C) is correct option. SOL 4.78 The circuit is as shown below V+ = 8 (3) = 8 k 1+8 3 V+ = V- = 8 V 3 Now applying KCL at inverting terminal we get V- 2 + V- Vo = 0 1 5 or Vo = 6V- 10 = 6 # 8 10 = 6 V 3 Hence (B) is correct option. Page 250 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.79 The equivalent circuit of 3 cascade stage is as shown in fig. V2 = 1k 50V1 = 40V1 1k + 0.25k Similarly V3 = 1k 50V2 = 40V2 1k + 0.25k or V3 = 40 # 40V1 Vo = 50V3 = 50 # 40 # 40V1 AV = Vo = 50 # 40 # 40 = 8000 V1 or 20 log AV = 20 log 8000 = 98 dB or Hence (C) is correct option. SOL 4.80 If a constant current is made to flow in a capacitor, the output voltage is integration of input current and that is sawtooth waveform as below : VC = 1 C # idt 0 t The time period of wave form is T = 1 = 1 = 2 m sec f 500 Thus or or 1 3= 2 # 106 20 # 10- 3 # idt 0 i (2 # 10 - 3 0) = 6 # 10 - 6 i = 3 mA Thus the charging require 3 mA current source for 2 msec. Hence (D) is correct option. Page 251 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.81 In voltage-amplifier or voltage-series amplifier, the Ri increase and Ro decrease because Rif = Ri (1 + A ) Ro Rof = (1 + A ) Hence (C) is correct option. SOL 4.82 Let x be the gain and it is 20 db, therefore 20 log x = 20 or x = 10 Since Gain band width product is 106 Hz, thus 6 6 So, bandwidth is BW = 10 = 10 = 105 Hz = 100 kHz 10 Gain Hence (B) is correct option. SOL 4.83 In multistage amplifier bandwidth decrease and overall gain increase. From bandwidth point of view only options (A) may be correct because lower cutoff frequency must be increases and higher must be decreases. From following calculation we have We have fL = 20 Hz and fH = 1 kHz For n stage amplifier the lower cutoff frequency is fL 20 f= = = 39.2 . 40 Hz Ln 1 2n 1 The higher cutoff frequency is 1 23 1 1 fHn = fH 2 2 1 = 0.5 kHz Hence (A) is correct option. SOL 4.84 As per Barkhousen criterion for sustained oscillations A $ 1 and phase shift must be or 2 n . V (f) Now from circuit A = O = 1 + R2 Vf (f) R1 V (f) (f) = 1 +0 = f 6 VO (f) Thus from above equation for sustained oscillation Page 252 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits 6 = 1 + R2 R1 or R2 = 5R1 Hence (A) is correct option. SOL 4.85 Let the gain of OPAMP be AV then we have 20 log AV = 40 dB or AV = 100 Let input be Vi = Vm sin t then we have VO = VV Vi = Vm sin t dVO = A V cos t Now Vm dt Slew Rate c dVO m = AV Vm = AV Vm 2 f dt max 1 or = -6 Vm = SR AV V2 f 10 # 100 # 2 # 20 # 103 or VM = 79.5 mV Hence (C) is correct option. SOL 4.86 The circuit is shown as below I = IZ + IL For satisfactory operations Vin V0 > I Z + IL R [IZ + IL = I] When Vin = 30 V, 30 10 $ (10 + 1) mA R 20 $ 11 mA or R or when Vin = 50 V R # 1818 Page 253 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits 50 10 $ (10 + 1) mA R 40 $ 11 # 10 - 3 R or R # 3636 Thus R # 1818 Hence (A) is correct option. SOL 4.87 We have Now and Thus Now = 10 mA and VP = 5 V =0 = ID RS = 1 # 2.5 = 2.5 V = VG VS = 0 2.5 = 2.5 V gm = 2IDSS 81 ` 2.5 jB = 2 mS VP 5 AV = V0 = gm RD Vi IDSS VG VS VGS So, = 2ms # 3k = 6 Hence (D) is correct option. SOL 4.88 The current gain of a BJT is hfe = gm r Hence (C) is correct option. SOL 4.89 The ideal op-amp has following characteristic : Ri " 3 R0 " 0 and A"3 Hence (A) is correct option. SOL 4.90 Both statements are correct because (1) A stable multivibrator can be used for generating square wave, because of its characteristic (2) Bi-stable multivibrator can store binary information, and this Page 254 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits multivibrator also give help in all digital kind of storing. Hence (C) is correct option. SOL 4.91 If fT is the frequency at which the short circuit common emitter gain attains unity magnitude then gm 38 # 10 - 3 = fT = 2 (C + C ) 2 # (10 - 14 + 4 # 10 - 13) or = 1.47 # 1010 Hz If fB is bandwidth then we have 10 f fB = T = 1.47 # 10 = 1.64 # 108 Hz 90 Hence (B) is correct option. SOL 4.92 If we neglect current through RB then it can be open circuit as shown in fig. Maximum power will dissipate in Zener diode when current through it is maximum and it will occur at Vin = 30 V I = Vin Vo = 30 10 = 1 A 20 20 or I IC + IZ = IB + IZ = IZ + IZ = ( + 1) IZ IZ = I = 1 = 0.01 A +1 99 + 1 Since IC = IB since IB = IZ Power dissipated in zener diode is PZ = VZ IZ = 9.5 # 0.01 = 95 mW IC = IZ = 99 # 0.1 = 0.99 A VCE = Vo = 10 V Power dissipated in transistor is PT = VC IC = 10 # 0.99 = 9.9 W Hence (C) is correct option. Page 255 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.93 From the it may be easily seen that the tank circuit is having 2-capacitors and one-inductor, so it is colpits oscillator and frequency is 1 f= 2 LCeq Ceq = C1 C2 = 2 # 2 = 1 pF 4 C1 + C2 9 1 = 1 # 10 = 50.3 MHz 2 10 2 10 # 10 - 6 # 10 - 12 Hence (B) is correct option. f= SOL 4.94 The circuit is as shown below Let V- be the voltage of inverting terminal, since non inverting terminal a at ground, the output voltage is ...(1) Vo = AOL VNow applying KCL at inverting terminal we have V- Vs + V- V0 = 0 ...(2) R1 R2 From (1) and (2) we have VO = A = R2 CL Vs R R2 + R1 ROL Substituting the values we have 10k = 1000 . 11 ACL = 10k + 1k 89 1k 100k Hence (D) is correct option. SOL 4.95 The first OPAMP stage is the differentiator and second OPAMP stage is integrator. Thus if input is cosine term, output will be also Page 256 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits cosine term. Only option (A) is cosine term. Other are sine term. However we can calculate as follows. The circuit is shown in fig Applying KCL at inverting terminal of first OP AMP we have V1 = jL = 100 # 10 # 10 - 3 = 1 R 10 10 VS or V1 = jVS = j cos 100t 10 Applying KCL at inverting terminal of second OP AMP we have VO = 1/j C 100 V1 = 1 = j10 j100 # 10 # 10 - 6 # 100 V0 = j10V2 = j10 ( j cos 100t) V0 = 10 cos 100t Hence (A) is correct option. or SOL 4.96 Common mode gain is AC = RC REE Since source resistance of the current source is infinite REE = 3 , common mode gain AC = 0 Hence (A) is correct option. SOL 4.97 In positive feed back it is working as OP-AMP in saturation region, and the input applied voltage is +ve. So, V0 =+ Vsat = 15 V Hence (D) is correct option. Page 257 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.98 With the addition of RE the DC abis currents and voltages remain closer to the point where they were set by the circuit when the outside condition such as temperature and transistor parameter change. Hence (C) is correct option. SOL 4.99 At high frequency gm + j (C) 1 Ai \ Capacitance Ai = or, and Ai ' gbc 1 frequency Thus due to the transistor capacitance current gain of a bipolar transistor drops. Hence (A) is correct option. SOL 4.100 As OP-AMP is ideal, the inverting terminal at virtual ground due to ground at non-inverting terminal. Applying KCL at inverting terminal sC (v1 sin t 0) + sC (V2 sin t 0) + sC (Vo 0) = 0 or Vo = (V1 + V2) sin t Hence (C) is correct option. SOL 4.101 There is R C , series connection in parallel with parallel R C combination. So, it is a wein bridge oscillator because two resistors R1 and R2 is also in parallel with them. Hence (D) is correct option. SOL 4.102 The given circuit is a differentiator, so the output of triangular wave will be square wave. Hence (A) is correct option. Page 258 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.103 In sampling and hold circuit the unity gain non-inverting amplifier is used. Hence (B) is correct option. SOL 4.104 The thevenin equivalent is shown below VT = R1 V = 5 # 15 = 5 V 10 + 5 R1 + R2 C Since is large is large, IC . IE , IB . 0 and IE = VT VBE RE 4.3 = 5 0.7 = = 10 mA 0.430k 0.430K Hence (D) is correct option. SOL 4.105 The output voltage will be input offset voltage multiplied by open by open loop gain. Thus So V0 = 5mV # 10, 000 = 50 V But V0 = ! 15 V in saturation condition So, it can never be exceeds ! 15 V So, V0 = ! Vset = ! 15V Hence (C) is correct option. SOL 4.106 Hence (A) is correct option. Page 259 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.107 Negative feedback in amplifier reduces the gain of the system. Hence (A) is correct option. SOL 4.108 By drawing small signal equivalent circuit by applying KCL at E2 V gm1 V = gm2 V r at C2 i 0 = gm2 V from eq (1) and (2) gm1 V + i 0 = i 0 gm2 r 2 2 1 2 2 1 2 gm1 V = i 0 :1 + 1 1 gm2 r D 2 gm2 r = >> 1 gm1 V = i 0 i 0 = g m1 V 2 so 1 1 i0 = g m1 Vi a V = Vi 1 Hence (A) is correct option. SOL 4.109 Crossover behavior is characteristic of calss B output stage. Here 2 transistor are operated one for amplifying +ve going portion and other for -ve going portion. Hence (B) is correct option. Page 260 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.110 In Voltage series feedback mode input impedance is given by R in = Ri (1 + v Av) where v = feedback factor , Av = openloop gain and Ri = Input impedance So, R in = 1 # 103 (1 + 0.99 # 100) = 100 k Similarly output impedance is given by R0 ROUT = R 0 = output impedance (1 + v Av) Thus ROUT = 100 = 1 (1 + 0.99 # 100) Hence (C) is correct option. SOL 4.111 Regulation = Vno load Vfuel load Vfull load = 30 25 # 100 = 20% 25 Output resistance = 25 = 25 1 Hence (B) is correct option. SOL 4.112 This is a voltage shunt feedback as the feedback samples a portion of output voltage and convert it to current (shunt). Hence (D) is correct option. SOL 4.113 In a differential amplifier CMRR is given by (1 + ) IQ R 0 CMRR = 1 ;1 + E 2 VT So where R 0 is the emitter resistance. So CMRR can be improved by increasing emitter resistance. Hence (A) is correct option. Page 261 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.114 We know that rise time (tr ) is tr = 0.35 fH where fH is upper 3 dB frequency. Thus we can obtain upper 3 dB frequency it rise time is known. Hence (C) is correct option. SOL 4.115 In a BJT differential amplifier for a linear response Vid < VT . Hence (D) is correct option. SOL 4.116 In a shunt negative feedback amplifier. Input impedance Ri R in = (1 + A) where Ri = input impedance of basic amplifier = feedback factor A = open loop gain So, R in < Ri Similarly R0 ROUT = (1 + A) ROUT < R 0 Thus input & output impedances decreases. Hence (D) is correct option. SOL 4.117 Hence (A) is correct option. SOL 4.118 Comparator will give an output either equal to + Vsupply or Vsupply . So output is a square wave. Hence (D) is correct option. Page 262 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.119 In series voltage regulator the pass transistor is in common collector configuration having voltage gain close to unity. Hence (C) is correct option. SOL 4.120 In bridge rectifier we do not need central tap transformer, so its less expensive and smaller in size and its PIV (Peak inverse voltage) is also greater than the two diode circuit, so it is also suitable for higher voltage application. Hence (D) is correct option. SOL 4.121 In the circuit we have V2 = IS # RD 2 and V1 = IS # RD V2 = 1 2 V1 V1 = 2V2 Hence (C) is correct option. SOL 4.122 Hence (C) is correct option. SOL 4.123 The equivalent circuit of given amplifier circuit (when CE is connected, RE is short-circuited) Input impedance Ri = R B | | r Voltage gain AV = gm RC Now, if CE is disconnected, resistance RE appears in the circuit Page 263 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits Input impedance R in = RB | | [r + ( + 1)] RE Input impedance increases gm RC Voltage gain decreases. Voltage gain AV = 1 + gm R E Hence (C) is correct option. SOL 4.124 In common emitter stage input impedance is high, so in cascaded amplifier common emitter stage is followed by common base stage. Hence (A) is correct option. SOL 4.125 We know that collect-emitter break down voltage is less than compare to collector base breakdown voltage. BVCEO < BVCBO both avalanche and zener break down. Voltage are higher than BVCEO .So BVCEO limits the power supply. Hence (C) is correct option. SOL 4.126 If we assume consider the diode in reverse bias then Vn should be greater than VP . VP < Vn by calculating Page 264 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits VP = 10 # 4 = 5 Volt 4+4 Vn = 2 # 1 = 2 Volt here VP > Vn (so diode cannot be in reverse bias mode). apply node equation at node a Va 10 + Va + Va = 2 1 4 4 6Va 10 = 8 Va = 3 Volt Ib = 0 3 + 10 3 4 4 Ib = 10 6 = 1 amp 4 so current Hence (C) is correct option. SOL 4.127 By applying node equation at terminal (2) and (3) of OP -amp Va Q Va V0 =0 + 5 10 2Va 4 + Va V0 = 0 V0 = 3Va 4 Va V0 + Va 0 = 0 100 10 Va V0 + 10Va = 0 Page 265 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits 11Va = V0 Va = V0 11 V0 = 3V0 4 11 So 8V0 = 4 11 V0 = 5.5 Volts Hence (D) is correct option. SOL 4.128 Circuit with diode forward resistance looks So the DC current will IDC = Vm (R f + RL) Hence (B) is correct option. SOL 4.129 For the positive half cycle of input diode D1 will conduct & D2 will be off. In negative half cycle of input D1 will be off & D2 conduct so output voltage wave from across resistor (10 k ) is Ammeter will read rms value of current so I rms = Vm (half wave rectifier) R = 4 = 0.4 mA (10 k ) Hence (D) is correct option. Page 266 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.130 In given circuit positive feedback is applied in the op-amp., so it works as a Schmitt trigger. Hence (D) is correct option. SOL 4.131 Gain with out feedback factor is given by V0 = kVi after connecting feedback impedance Z given input impedance is very large, so after connecting Z we have Ii = Vi V0 V0 = kVi Z Ii = Vi kVi Z input impedance Zin = Vi = Z Ii (1 k) Hence (D) is correct option SOL 4.132 Hence (A) is correct option. SOL 4.133 For the circuit, In balanced condition It will oscillated at a frequency 1 = 1 = = 105 rad/ sec 3 6 LC 10 # 10 # .01 # 10 In this condition R1 = R 3 R2 R4 5 =R 100 1 R = 20 k = 2 # 10 4 Hence (A) is correct option. Page 267 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236 www.gatehelp.com Chap 4 Analog Circuits SOL 4.134 V0 kept constant at so current in 50 resistor V0 = 6 volt I = 9 6 50 I = 60 m amp Maximum allowed power dissipation in zener PZ = 300 mW Maximum current allowed in zener PZ = VZ (IZ ) max = 300 # 10 3 & = 6 (IZ ) max = 300 # 10 3 & = (IZ ) max = 50 m amp Given knee current or minimum current in zener (IZ ) min = 5 m amp In given circuit I = IZ + I L I L = I IZ (IL) min = I (IZ ) max = (60 50) m amp = 10 m amp (IL) max = I (IZ ) min = (60 5) = 55 m amp Hence (C) is correct option. *********** Page 268 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY Visit us at: www.nodia.co.in ISBN: 9788192276236

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