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Dataflow Verilog ECEn 224 A2 VERILOG Page 1 2003-2008 BYU Motivation Structural design can be cumbersome Lots of typing 32-bit busses & logic Structural designs are static At least in Verilog (not so for VHDL) Little or no parameterization possible ECEn 224 A2 VERILOG Page 2 2003-2008 BYU A Dataflow MUX Version 1 module mux21(q, sel, a, b); input sel, a, b; output q; assign q = (~sel & a) | (sel & b); endmodule Much simpler, less typing, familiar C-like syntax. Synthesizer turns it into optimized gate-level design. ECEn 224 A2 VERILOG Page 3 2003-2008 BYU A Dataflow MUX Version 2 module mux21(q, sel, a, b); input sel, a, b; output q; assign q = sel ? b : a; endmodule Even simpler, uses C-like ternary ( ?: ) construct ECEn 224 A2 VERILOG Page 4 2003-2008 BYU Dataflow Operators Operator Type Operator Symbol Arithmetic *, /, +, % Logical ! && || Bitwise ~ & | ^ ~^ Relational <, >, <=, >= Equality ==, != Reduction & ~& | ~| ^ ~^ Shift << >> Concat {} Replicate { { } } Cond ?: Operation Performed As expected Modulo Logic NOT Logic AND Logic OR Bitwise NOT Bitwise AND Bitwise OR Bitwise XOR Bitwise XNOR As expected As expected Red. AND Red. NAND Red. OR Red. NOR Red. XOR Red. XNOR Left shift Right shift Concatenate Replicate As expected ECEn 224 # of Operands Comments * and / take LOTS of 2 hardware 2 1 As in C 2 As in C 2 As in C 1 As in C 2 As in C 2 As in C 2 As in C 2 2 As in C 2 As in C 1 Multi-bit input 1 Multi-bit input 1 Multi-bit input 1 Multi-bit input 1 Multi-bit input 1 Multi-bit input 2 Fill with 0's 2 Fill with 0's Any number Any number 3 As in C A2 VERILOG Page 5 2003-2008 BYU Bitwise vs. Logic Operators Similar to C assign q = ((a<4 b1101) && ((c&4 b0011)!=0)) ? 1 b0:1 b1; Pseudo-code (not real Verilog): if (a<4 b1101 && (c&4 b0011) != 0) then q <= 0 ; else 4 q <= 1 ; c 0011 4 4 a 1101 < 1 q 4 1 4 Use &&, ||, ! for 1-bit quantities (results of comparisions) Use &, |, ~ for bit-by-bit logical operations ECEn 224 A2 VERILOG Page 6 2003-2008 BYU Reduction Operators wire[3:0] x; wire z; assign z = &x; // Same as z = x[3] & x[2] & x[1] & x[0] ECEn 224 A2 VERILOG Page 7 2003-2008 BYU Concatenation and Replication Operators wire[3:0] x, y; wire[7:0] z, q, w, t; wire[31:0] m, n; assign assign assign assign assign assign assign x y z q w t m = 4 b1100; = 4 b0101; = {x, x}; // z is 8 b11001100 = {x, y}; // q is 8 b11000101 = {4 b1101, y}; // w is 8 b11010101 = {2{x}}; // same as {x, x} = {{4{x}}, {2{q}}}; // m is 32 b11001100110011001100010111000101 ECEn 224 A2 VERILOG Page 8 2003-2008 BYU Operator Precedence Similar to C Higher precedence Unary -, unary +, !, ~ *, /, % +, <<, >> <, <=, >, >= ==, != &, ~& ^, ~^ |, ~| && || ?: Lower precedence ECEn 224 A2 VERILOG Page 9 2003-2008 BYU A Note on Matching Widths This a valid 2:1 MUX statement: wire a, b, sel, q; assign q = (~sel & a) | (sel & b); But the following is not: wire[3:0] a, b, q; wire sel; assign q = (~sel & a) | (sel & b); Why? ECEn 224 A2 VERILOG Page 10 2003-2008 BYU More On Matching Wire Widths This is an acceptable substitute: wire[3:0] a, b, q; wire sel; assign q = ({4{~sel}}&a)|({4{sel}}&b); It turns the sel and ~sel values into 4-bit versions for AND-ing and OR-ing A more elegant version: wire[3:0] a, b, q; wire sel; assign q = sel ? b: a; ECEn 224 A2 VERILOG Page 11 2003-2008 BYU Design Example: A 2:4 Decoder module decode24(q, a); output[3:0] q; input[1:0] a; assign q = (4 b0001) << a; endmodule Can you see how to make a 3:8 or 4:16 decoder in the same fashion? ECEn 224 A2 VERILOG Page 12 2003-2008 BYU Multi-bit Design and Parameterization ECEn 224 A2 VERILOG Page 13 2003-2008 BYU A Dataflow MUX Multi-Bit module mux21(q, sel, a, b); input sel; input[15:0] a, b; output[15:0] q; assign q = sel ? b : a; endmodule a 16 16 b 0 16 q 1 s Key Ideas: The predicate must evaluate to true or false (1 or 0) The parts getting assigned must be all same widths. ECEn 224 A2 VERILOG Page 14 2003-2008 BYU A Dataflow MUX Parameterized Width module mux21n(q, sel, a, b); parameter WID = 16; input sel; input[WID-1:0] a, b; output[WID-1:0] q; assign q = sel ? b : a; endmodule By default, this is now a 16-bit wide MUX. When instantiating, the default value of 16 can be overridden: mux21n M1(q, sel, a, b); mux21n #(4) M0(q, sel, a, b); // Instance a 16-bit version // Instance a 4-bit version Does this work for a 1-bit MUX? ECEn 224 A2 VERILOG Page 15 2003-2008 BYU Using Parameterization Careful planning often allows you to write one design which can be reused Reuse is a common goal in design Simplifies your work Eliminates errors Saves time later Whenever possible, plan for reuse ECEn 224 A2 VERILOG Page 16 2003-2008 BYU Parameterization Exercise Design a 4:1 MUX that works with any size operands (arbitrary bit-width) Either: Build arbitrary bit-width 2:1 MUX Structurally instance 3 of these to make a 4:1 MUX or Write an arbitrary bit-width 4:1 MUX using the ?: operator ECEn 224 A2 VERILOG Page 17 2003-2008 BYU 4:1 MUX Method 1 module mux41n(q, sel, a, b, c, d); parameter WID=16; input[1:0] sel; input[WID-1:0] a, b, c, d; output[WID-1:0] q; wire[WID-1:0] tmp1, tmp2; mux21n #(WID) M0(tmp1, sel[0], a, b); mux21n #(WID) M1(tmp2, sel[0], c, d); mux21n #(WID) M2(q, sel[1], tmp1, tmp2); endmodule If the mux21n cells are parameterizable for bit-width this works If not, it doesn t work ECEn 224 A2 VERILOG Page 18 2003-2008 BYU 4:1 MUX Method 2 module mux41(q, sel, a, b, c, d); parameter WID=16; input[1:0] sel; input[WID-1:0] a, b, c, d; output[WID-1:0] q; assign q = (sel==2'b00) ? a: (sel==1) ? b: (sel==2 b10) ? c: d; endmodule Cascaded ?: operators form an if-then-else structure Note how sel can be compared to bit patterns (2 b00) or to numbers (1) ECEn 224 A2 VERILOG Page 19 2003-2008 BYU Behavioral Verilog ECEn 224 A2 VERILOG Page 20 2003-2008 BYU Used for Sequential Circuits and Combinational Circuits module dff(clk, d, q); input clk, d; output reg q; always @(posedge clk) q <= d; endmodule You can use this as a DFF for your design. Figure out how to parameterize it for arbitrary input/output widths Remainder of behavioral design not covered in this class ECEn 224 A2 VERILOG Page 21 2003-2008 BYU Conclusion With what you know You can do reasonable designs Must structurally instance all storage elements (flip flops) Behavioral Design A number of nuances with respect to timing semantics Not recommended beyond simple FF s for this class You will learn full range of behavioral design in later courses ECEn 224 A2 VERILOG Page 22 2003-2008 BYU

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