Trending ▼   ResFinder  

1997 Course Digital System Design

3 pages, 21 questions, 0 questions with responses, 0 total responses,    0    0
pune_eng
   		+Fave Message
ProfileTimelineUploadsQ & A
 Home > pune_eng >

Formatting page ...

Total No. of Questions : 8] [Total No. of Pages : 3 P1460 [3764]-1092 B.E. (Computer) DIGITAL SYSTEM DESIGN (1997 Course) Time : 3 Hours] [Max. Marks : 100 Instructions to the candidates : 1) Answer any three questions from each section. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams must be drawn wherever necessary. 4) Figures to the right indicate full marks. 5) Assume suitable data, if necessary. SECTION - I Q1) a) Explain in brief the architecture of CPLD with the help of block diagram. [8] b) Write VHDL code for FSM shown in the following figure. [10] P.T.O.

Formatting page ...

Formatting page ...

 

  Print intermediate debugging step

Show debugging info


 


Tags : Pune, Engineering, University of Pune, Engineering question papers, Pune University, previous year question papers, question papers, india, model question paper, pune university paper pattern, pune university syllabus, old question papers  

© 2010 - 2024 ResPaper. Terms of ServiceContact Us Advertise with us

 

pune_eng chat