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7/4/12 Asynchronous Counter as a Decade Counter Sear c h: LINKS Hom e Site Map Se ar ch Sit e Electronics Tutorial about Asynchronous Counters Do you like our Site? Help us to Share It 3 Asynchronous Counter Navigation Site Search Like 1. 2k - - - Selec t a Tutor ial Page - - - Link Partners Blogs pot Books tore Contact Us Calculators & Tools Trac e W idth Trac e Current Trac e Res is tanc e PCB Impedanc e 4 Band Res is tor 5 Band Res is tor 6 Band Res is tor Res is tor Table Induc tanc e Calc Coil Induc tanc e Parallel W ires Impedanc e Matc h RF Unit Converter Coax Impedanc e Twis ted Pair Cros s talk Calc Graph Paper Engineering Calc Go Re s e t Tu t o r i a l : 2 o f 4 A s ync hr o no us C o unt e r In the previous tutorial we s aw that an Asynchronous counter can have 2n-1 pos s ible counting s tates e.g. MOD-16 for a 4-bit counter, (0-15) m aking it ideal for us e in Fre que ncy Di vi si on. But it is als o pos s ible to us e the bas ic as ynchronous counter to cons truct s pecial counters with counting s tates les s than their m axim um output num ber by forcing the counter to res et its elf to zero at a pre-determ ined value producing a type of as ynchronous counter that has truncated s equences . Then an n-bit counter that counts up to its m axim um m odulus (2n) is called a full s equence counter and a n-bit counter whos e m odulus is les s than the m axim um pos s ible is called a truncated counter. But why would we want to create an as ynchronous truncated counter that is not a MOD-4, MOD-8, or s om e other m odulus that is equal to the power of two. The ans wer is that we can by us ing com binational logic to take advantage of the as ynchronous inputs on the flip-flop. If we take the m odulo-16 as ynchronous counter and m odified it with additional logic gates it can be m ade to give a decade (divide-by-10) counter output for us e in s tandard decim al counting and arithm etic circuits . Such counters are generally referred to as Decade Counters. A decade counter requires res etting to zero when the output count reaches the decim al value of 10, ie. when DCBA = 1010 and to do this we need to feed this condition back to the res et input. A counter with a count s equence from binary "0000" (BCD = "0") through to "1001" (BCD = "9") is generally referred to as a BCD binary-coded-decim al counter becaus e its ten s tate s equence is that of a BCD code but binary decade counters are m ore com m on. Asynchronous De ca de Counte r This type of as ynchronous counter counts upwards on each leading edge of the input clock s ignal s tarting from "0000" until it reaches an output "1010" (decim al 10). Both outputs QB and QD are now equal to logic "1" and the output from the NAND gate changes s tate from logic "1" to a logic "0" level and whos e output is als o connected to the CLEAR (CLR) inputs of all the J-K Flip-flops . This caus es all of the Q outputs to be res et back to binary "0000" on the count of 10. Once QB and QD are both equal to logic "0" the output of the NAND gate returns back to a logic level "1" and the counter res tarts again from "0000". We now have a decade or Modulo-10 counter. De ca de Counte r Truth Ta ble Cloc k Count 1 2 3 4 5 6 www.electronics-tutorials.ws/counter/count_2.html Output bit Pattern QD QC QB QA 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Dec imal Value 0 1 2 3 4 5 1/3 7/4/12 Asynchronous Counter as a Decade Counter 6 0 1 0 1 5 7 0 1 1 0 6 8 0 1 1 1 7 9 1 0 0 0 8 10 1 0 0 1 9 11 Counter Res ets its Outputs bac k to Zero De ca de Counte r Tim ing Dia gra m Us ing the s am e idea of truncating counter output s equences , the above circuit could eas ily be adapted to other counting cycles be s im ply changing the connections to the AND gate. For exam ple, a s cale-oftwelve (m odulo-12) can eas ily be m ade by s im ply taking the inputs to the AND gate from the outputs at "QC" and "QD", noting that the binary equivalent of 12 is "1100" and that output "QA" is the leas t s ignificant bit (LSB). Since the m axim um m odulus that can be im plem ented with n flip-flops is 2n, this m eans that when you are des igning truncated counters you s hould determ ine the lowes t power of two that is greater than or equal to your des ired m odulus . For exam ple, lets s ay you wis h to count from 0 to 39, or m od-40. Then the highes t num ber of flip-flops required would be s ix, n = 6 giving a m axim um MOD of 64 as five flip-flops would only equal MOD-32. Then s uppos e we wanted to build a "divide-by-128" counter for frequency divis ion we would need to 7 cas cade s even flip-flops s ince 128 = 2 . Us ing dual flip-flops s uch as the 74LS74 we would s till need four IC's to com plete the circuit. One eas y alternative m ethod would be to us e two TTL 7493's as 4-bit ripple counter/dividers . Since 128 = 16 x 8, one 7493 could be configured as a "divide-by-16" counter and the other as a "divide-by-8" counter. The two IC's would be cas caded together to form a "divide-by-128" frequency divider as s hown. Of cours e s tandard IC as ynchronous counters are available s uch as the TTL 74LS90 program m able ripple counter/divider which can be configured as a divide-by-2, divide-by-5 or any com bination of both. The 74LS390 is a very flexible dual decade driver IC with a large num ber of "divide-by" com binations available ranging form divide-by-2, 4, 5, 10, 20, 25, 50, and 100. Frequency Dividers This ability of the ripple counter to truncate s equences to produce a "divide-by-n" output m eans that counters and es pecially ripple counters , can be us ed as frequency dividers to reduce a high clock frequency down to a m ore us able value for us e in digital clocks and tim ing applications . For exam ple, as s um e we require an accurate 1Hz tim ing s ignal to operate a digital clock. We could quite eas ily produce a 1Hz s quare wave s ignal from a s tandard 555 tim er chip but the m anufacturers data s heet tells us that it has a typical 1-2% tim ing error depending upon the m anufacturer, and at low frequencies a 2% error at 1Hz is not good. However the data s heet als o tells us that the m axim um operating frequency of the 555 tim er is about 300kHz and a 2% error at this high frequency would be acceptable. So by choos ing a higher tim ing frequency of s ay 262.144kHz and an 18-bit ripple (Modulo-18) counter we can m ake a precis ion 1Hz tim ing s ignal as s hown below. Sim ple 1Hz tim ing signa l using a n 18-bit ripple counte r/divide r. www.electronics-tutorials.ws/counter/count_2.html 2/3 7/4/12 Asynchronous Counter as a Decade Counter This is of cours e a very s im ple exam ple of how to produce accurate frequencies , but by us ing high frequency crys tal os cillators and m ulti-bit frequency dividers , precis ion frequency generators can be produced for for a range of applications ranging from clocks or watches to event tim ing and even electronic piano/s ynthes izer m us ic applications . The m ain dis advantages with as ynchronous counters are that there is a s m all delay between the arrival of the clock puls e and its output due to the internal circuitry of the gate. In as ynchronous circuits this delay is called the Propagation Delay (giving the as ynchronous ripple counter the nicknam e of propagation counter) and in s om e cas es can produce fals e output counts . In large bit ripple counter circuits the delay of all the s eparate s tages are added together to give a s um m ed delay at the end of the chain which is why as ynchronous counters are generally not us ed for in high frequency counting circuits were large num bers of bits are involved. Als o, the outputs from the counter do not have a fixed tim e relations hip with each other and do not occur at the s am e tim e due to their clocking s equence. Then, the m ore flip-flops that are added to an as ynchronous counter chain the lower the m axim um operating frequency becom es . To overcom e the problem of propagation delay Sy nc hronous Count ers were developed. Then to s um m aris e: Asynchronous Counters can be m ade from Toggle or D-type flip-flops . They are called as ynchronous counters becaus e the clock input of the flip-flops are not all driven by the s am e clock s ignal. Each output in the chain depends on a change in s tate from the previous flip-flops output. As ynchronous counters are s om etim es called ripple counters becaus e the data appears to "ripple" from the output of one flip-flop to the input of the next. They can be im plem ented us ing "divide-by-n" circuits . Truncated counters can produce any m odulus num ber count. Dis advantages of As ynchronous Counters : An extra "re-s ynchronizing" output flip-flop m ay be required. To count a truncated s equence not equal to 2n, extra feedback logic is required. Counting a large num ber of bits , propagation delay by s ucces s ive s tages m ay becom e u n d e s i ra b l y l a rg e . This delay gives them the nicknam e of "Propagation Counters ". Counting errors at high clocking frequencies . Synchronous Counters are fas ter us ing the s am e clock s ignal for all flip-flops . In the next tutorial about Count ers , we will look at the Synchronous Counte r and s ee that the m ain characteris tic of an s ynchronous counter is that the clock input of each flip-flop in the chain is connected to all of the flip-flops s o that they are clocked s im ultaneous ly. Goto Page: 1 2 3 4 Bas ic Elec tr onic s Tutor ials by Way ne Stor r . Las t updated: July 2012 , Copy r ight 1999 2012, Elec tr onic s - Tutor ials .w s , A ll Right Res er v ed. | Priv ac y Polic y | Terms of Us e | Site Map | Contac t Us | Bas ic Elec tronic s Tutorials | www.electronics-tutorials.ws/counter/count_2.html 3/3

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